The present invention is generally directed to operational amplifiers, and more specifically, to a low-supply voltage operational amplifier that drives large currents with rail-to-rail output voltages.
Increasingly, electronic devices are designed to operate from ever smaller power supply voltages. Smaller supply voltages are designed to minimize leakage currents and other undesirable effects that increase at smaller transistor sizes (e.g., 0.18 microns). Smaller supply voltages also save power, which is an especially important consideration in portable devices that operate from a battery. For example, current cellular telephones and other portable applications operate from a +1.8 volt power supply rail.
However, problems are encountered as power supply voltage levels become ever smaller. In applications where a given amount of power is required, the trend toward smaller supply voltages means that the current requirement must be increased to offset the reduced power supply voltage. For example, in a cellular telephone, a given amount of power is required to drive the speaker to an audible level. To maintain this power level, the current driving the speaker must increase as the output voltage decreases. The impedance of the speaker becomes smaller with the supply voltage in order to maintain the output power due to a larger current.
But difficulties are encountered when trying to combine a rail-to-rail output voltage range (0 to 1.8 volts) with a large output current (e.g., 60 mA). In order to drive a large current with a small drain-source voltage, V(ds), as is the case with the output transistors of a speaker driver, large W/L (channel width (W) to channel length (L) ratio) values are needed. As a result, the quiescent gate-source voltages V(gs) of these transistors tend to become very small in order to keep the quiescent current, I(q), acceptably small.
However, if a class-AB push-pull operational amplifier (op-amp) drives the speaker, the V(gs) of the push-pull transistors of the output stage should be at least larger than one saturation voltage V(dssat) of the output transistors of the previous stage, in order to maintain their high output resistance and thus the voltage gain of the first stage. Thus, large output transistors become very difficult (or even impossible) to bias in a conventional class-AB operational amplifier (op-amp) with an acceptably small quiescent current, I(q).
Therefore there is a need in the art for improved operational amplifier that are able to operate from small power supply voltage levels while still driving large output currents. In particular, there is a need for an op-amp that operates from a +1.8 volt power supply, that drives a large amount of current, and that has a small quiescent current.
The present invention provides an improved operational amplifier that solves the above-described problem of using standard class-AB power amplifiers at low supply voltages (e.g., +1.8 volts). The present invention comprises a class-AB stage followed by a class B current booster stage. The present invention divides the output transistors into relatively large class-B output drivers in parallel with relatively small class-AB transistors. The small class-AB transistors have a minimum quiescent transconductance, whereas the class-B current booster transistors are inactive in the quiescent state and only deliver large currents for output voltages approaching the power supply rails.
The class-B current booster stage has minimum impact on the class-AB amplifier stage and can be adjusted independently whenever larger currents are needed in future applications. Furthermore, the transistors of the class-B current booster do not have to match in any way with other transistors and are therefore easy to handle in layout.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide an improved operational amplifier. According to an advantageous embodiment of the present invention, the operational amplifier comprises: 1) a class-AB push-pull stage comprising a first P-channel output transistor and a first N-channel output transistor for driving an output load; and 2) a class-B current booster stage coupled in parallel with the class-AB push-pull stage comprising a second P-channel output transistor and a second N-channel output transistor for driving the output load.
According to one embodiment of the present invention, the first P-channel output transistor and the first N-channel output transistor have a minimum quiescent transconductance level.
According to another embodiment of the present invention, the second P-channel output transistor and the second N-channel output transistor are biased so that the second P-channel output transistor and the second N-channel output transistor are inactive in the quiescent state.
According to still another embodiment of the present invention, the second P-channel output transistor turns on as an output voltage of the operational amplifier increases towards a positive power supply fail.
According to yet another embodiment of the present invention, the second P-channel output transistor is capable of driving a larger current into the output load than the first P-channel output transistor.
According to a further embodiment of the present invention, the second P-channel output transistor is coupled to the first P-channel output transistor by a coupling P-channel transistor, wherein a gate of the coupling P-channel output transistor is coupled to a gate of the first P-channel output transistor and a source of the coupling P-channel output transistor is coupled to a gate of the second P-channel output transistor.
According to a still further embodiment of the present invention, the second N-channel output transistor turns on as an output voltage of the operational amplifier decreases towards a negative power supply fail.
According to a yet further embodiment of the present invention, the second N-channel output transistor is capable of sinking a larger current from the output load than the first N-channel output transistor.
In one embodiment of the present invention, the second N-channel output transistor is coupled to the first N-channel output transistor by a coupling N-channel transistor, wherein a gate of the coupling N-channel output transistor is coupled to a gate of the first N-channel output transistor and a source of the coupling N-channel output transistor is coupled to a gate of the second N-channel output transistor.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.